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Power Distribution Controllers
ISL6115, ISL6116, ISL6117, ISL6120
This family of fully featured hot swap power controllers targets applications in the +2.5V to +12V range. The ISL6115 is for +12V control, the ISL6116 for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V control applications. Each has a hard wired undervoltage (UV) monitoring and reporting threshold level approximately 80% of the aforementioned voltage. The ISL6115 has an integrated charge pump allowing control of up to +16V rails using an external N-Channel MOSFET whereas the other devices utilize the +12V bias voltage to fully enhance the N-Channel pass FET. All ICs feature programmable overcurrent (OC) detection, current regulation (CR) with time delay to latch-off and soft-start. The current regulation level is set by 2 external resistors; RISET sets the CR Vth and the other is a low ohmic sense element across, which the CR Vth is developed. The CR duration is set by an external capacitor on the CTIM pin, which is charged with a 20A current once the CR Vth level is reached. If the voltage on the CTIM capacitor reaches 1.9V the IC then quickly pulls down the GATE output latching off the pass FET. This family although designed for high side switch control the ISL6116, ISL6117, ISL6120 can also be used in a low side configuration for control of much higher voltage potentials.
ISL6115, ISL6116, ISL6117, ISL6120
Features
* HOT SWAP Single Power Distribution Control (ISL6115 for +12V, ISL6116 for +5V, ISL6117 for +3.3V and ISL6120 for +2.5V) * Overcurrent Fault Isolation * Programmable Current Regulation Level * Programmable Current Regulation Time to Latch-Off * Rail-to-Rail Common Mode Input Voltage Range (ISL6115) * Internal Charge Pump Allows the Use of N-Channel MOSFET for +12V Control (ISL6115) * Undervoltage and Overcurrent Latch Indicators * Adjustable Turn-On Ramp * Protection During Turn-On * Two Levels of Overcurrent Detection Provide Fast Response to Varying Fault Conditions * 1s Response Time to Dead Short * Pb-Free Available (RoHS Compliant)
Applications
* Power Distribution Control * Hot Plug Components and Circuit
Application Circuits- High Side Controller
+ LOAD -
Application Two - Low Side Controller
+VBUS LOAD
1 2 3 4
8
ISL6115 ISL6116 ISL6117 ISL6120
PWRON 7 6 OC 5 4 3 2 1 PGOOD
ISL6116 ISL6117 ISL6120
5 6 7 8
PWRON
+V SUPPLY TO BE CONTROLLED
+12V
12V REG OC
April 29, 2010 FN9100.7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004-2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6115, ISL6116, ISL6117, ISL6120
Simplified Block Diagram
VDD + ISET + + ISEN UV + -
POR
8V
QN R R Q S
PWRON
VREF ENABLE 12V PGOOD 20A CLIM + + WOCLIM ENABLE 20A RISING EDGE PULSE VDD 7.5k + 1.86V + -
ISL61xx UV DISABLE OC GATE 10A 18V
FALLING EDGE DELAY
CTIM
VSS
18V
Pin Configuration
ISL6115, ISL6116, ISL6117, ISL6120 (8 LD SOIC) TOP VIEW
ISET ISEN GATE VSS 1 2 3 4 8 PWRON 7 PGOOD 6 CTIM 5 VDD
Ordering Information
PART NUMBER ISL6115CB (Note 1) ISL6115CBZA (Notes 1, 2) ISL6116CBZA (Notes 1, 2) ISL6117CBZA (Notes 1, 2) ISL6120CBZA (Notes 1, 2) ISL6115EVAL1Z NOTES: 1. Please refer to TB347 for details on reel specifications. Add "-T" suffix for tape and reel. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6115. For more information on MSL please see techbrief TB363. PART MARKING ISL61 15CB 6115 CBZ 6116 CBZ 6117 CBZ 6120 CBZ Evaluation Platform TEMP. RANGE (C) 0 to +85 0 to +85 0 to +85 0 to +85 0 to +85 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Pin Descriptions
PIN # SYMBOL 1 2 3 ISET ISEN GATE FUNCTION Current Set Current Sense External FET Gate Drive Pin Chip Return Chip Supply Current Limit Timing Capacitor 12V chip supply. This can be either connected directly to the +12V rail supplying the switched load voltage or to a dedicated VSS +12V supply. Connect a capacitor from this pin to ground. This capacitor determines the time delay between an overcurrent event and chip output shutdown (current limit time-out). The duration of current limit time-out is equal to 93k x CTIM. DESCRIPTION Connect to the low side of the current sense resistor through the current limiting set resistor. This pin functions as the current limit programming pin. Connect to the more positive end of sense resistor to measure the voltage drop across this resistor. Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets the turn-on ramp. At turn-on this capacitor will be charged to VDD +5V (ISL6115) and to VDD (ISL6116, ISL6117, ISL6120) by a 10A current source.
4 5 6
VSS VDD CTIM
7
PGOOD
Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for the particular IC. Power-ON PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip is reset by a low level signal applied to this pin. This input has 20A pull-up capability.
8
PWRON
3
FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Absolute Maximum Ratings TA = +25C
VDD . . . . . . . . . . . . . . . . . . GATE . . . . . . . . . . . . . . . . . ISEN, PGOOD, PWRON, CTIM, ESD Rating Human Body Model . . . . . . . . . . . . . . . . . -0.3V to +16V . . . . . . . . . -0.3V to VDD + 8V ISET . . . -0.3V to VDD + 0.3V . . . . . . . . . . . . . . . . . . . 5kV
Thermal Information
Thermal Resistance (Typical, Note 4) JA (C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature (Plastic Package) . . +150C Maximum Storage Temperature Range . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
VDD Supply Voltage Range (ISL6115) . . . . . . . . +12V 15% VDD Supply Voltage Range (ISL6116, 17, 20) . . +12V 25% Temperature Range (TA) . . . . . . . . . . . . . . . . 0C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
VDD = 12V, TA = TJ = 0C to +85C, Unless Otherwise Specified. Temperature limits established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS
PARAMETER CURRENT CONTROL ISET Current Source ISET Current Source Current Limit Amp Offset Voltage Current Limit Amp Offset Voltage GATE DRIVE GATE Response Time to Severe OC GATE Response Time to Overcurrent GATE Turn-On Current GATE Pull-Down Current GATE Pull-Down Current (Note 6) ISL6115 Undervoltage Threshold ISL6115 GATE High Voltage ISL6116 Undervoltage Threshold ISL6117 Undervoltage Threshold ISL6120 Undervoltage Threshold ISL6116, ISL6117, ISL6120 GATE High Voltage BIAS VDD Supply Current VDD POR Rising Threshold VDD POR Falling Threshold VDD POR Threshold Hysteresis Maximum PWRON Pull-Up Voltage
IISET_ft IISET_pt Vio_ft Vio_pt TJ = +15C to +55C VISET - VISEN VISET - VISEN, TJ = +15C to +55C
18.5 19 -6 -2
20 20 0 0
21.5 21 6 2
A A mV mV
pd_woc_amp pd_oc_amp IGATE OC_GATE_I_4V
VGATE to 10.8V VGATE to 10.8V VGATE to = 6V Overcurrent
8.4 45 0.5 9.2
100 600 10 75 0.8 9.6
11.6 10 4.5 2.8 1.9 -
ns ns A mA A V V V V V V
WOC_GATE_I_4V Severe Overcurrent 12VUV_VTH 12VG 5VUV_VTH 3VUV_VTH 2VUV_VTH VG GATE Voltage GATE Voltage
VDD + 4.5V VDD + 5V 4.0 2.4 1.8 VDD - 1.5V 4.35 2.6 1.85 VDD
IVDD VDD_POR_L2H VDD_POR_H2L VDD_POR_HYS PWRN_PUV VDD Low to High VDD High to Low VDD_POR_L2H - VDD_POR_H2L Maximum External Pull-up Voltage
7.8 7.5 0.1 -
3 8.4 8.1 0.3 5
5 9 8.7 0.6 -
mA V V V V
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Electrical Specifications
VDD = 12V, TA = TJ = 0C to +85C, Unless Otherwise Specified. Temperature limits established by characterization and are not production tested. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) SYMBOL PWRN_V PWR_Vth PWR_hys PWRN_I TEST CONDITIONS PWRON Pin Open MIN (Note 7) 2.7 1.4 130 9 TYP 3.2 1.7 170 17 MAX (Note 7) UNITS 2.0 250 25 V V mV A
PARAMETER PWRON Pull-Up Voltage PWRON Rising Threshold PWRON Hysteresis PWRON Pull-Up Current
CURRENT REGULATION DURATION/POWER GOOD CTIM Charging Current CTIM Fault Pull-Up Current (Note 6) Current Limit Time-Out Threshold Voltage Power Good Pull Down Current NOTES: 6. Limits established by characterization and are not production tested. 7. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. CTIM_Vth PG_Ipd CTIM Voltage VOUT = 0.5V CTIM_ichg0 VCTIM = 0V 16 1.3 20 20 1.8 8 23 2.3 A mA V mA
Description and Operation
The members of this IC family are single power supply distribution controllers for generic hot swap applications across the +2.5V to +12V supply range. The ISL6115 is targeted for +12V switching applications whereas the ISL6116 is targeted for +5V, the ISL6117 for +3.3V and the ISL6120 for +2.5V applications. Each IC has a hardwired undervoltage (UV) threshold level approximately 17% lower than the stated voltages. These ICs feature a highly accurate programmable current regulation (CR) level with programmable time delay to latch-off, and programmable soft-start turnHon ramp all set with a minimum of external passive components. The ICs also include severe OC protection that immediately shuts down the MOSFET switch should a rapid load current transient such as with a dead short cause the CR Vth to exceed the programmed level by 150mV. Additionally, the ICs have a UV indicator and an OC latch indicator. The functionality of the PGOOD feature is enabled once the IC is biased, monitoring and reporting any UV condition on the ISEN pin. Upon initial power-up, the IC can either isolate the voltage supply from the load by holding the external N-Channel MOSFET switch off or apply the supply rail voltage directly to the load for true hot swap capability. The PWRON pin must be pulled low for the device to isolate the power supply from the load by holding the external N-Channel MOSFET off. With the PWRON pin held high or floating the IC will be in true hot swap mode. In both cases the IC turns on in a soft-start mode protecting the supply rail from sudden in-rush current.
At turn-on, the external gate capacitor of the NChannel MOSFET is charged with a 10A current source resulting in a programmable ramp (soft-start turn-on). The internal ISL6115 charge pump supplies the gate drive for the 12V supply switch driving that gate to ~VDD +5V, for the other three ICs the gate drive voltage is limited to the chip bias voltage, VDD. Load current passes through the external current sense resistor. When the voltage across the sense resistor exceeds the user programmed CR voltage threshold value, (see Table 1 for RISET programming resistor value and resulting nominal current regulation threshold voltage, VCR) the controller enters its current regulation mode. At this time, the time-out capacitor, on CTIM pin is charged with a 20A current source and the controller enters the current limit time to latch-off period. The length of the current limit time to latch-off duration is set by the value of a single external capacitor (see Table 2) for CTIM capacitor value and resulting nominal current limited time-out to latch-off duration placed from the CTIM pin (pin 6) to ground. The programmed current level is held until either the OC event passes or the time-out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM capacitor is discharged. Once CTIM charges to 1.87V signaling that the time-out period has expired, an internal latch is set whereby the FET gate is quickly pulled to 0V turning off the N-Channel MOSFET switch, isolating the faulty load.
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 1. RISET PROGRAMMING RESISTOR VALUE RISET RESISTOR 10k 4.99k 2.5k 750 NOTE: Nominal Vth = RISET x 20A. TABLE 2. CTIM CAPACITOR VALUE CTIM CAPACITOR 0.022F 0.047F 0.1F NOMINAL CURRENT LIMITED PERIOD 2ms 4.4ms 9.3ms NOMINAL CR VTH 200mV 100mV 50mV 15mV
external N-Channel MOSFET is reduced driving the MOSFET switch into a (linear region) high rDS(ON) state. Strike a balance between the CR limit and the timing requirements to avoid periods when the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET SOA information in the manufacturer's data sheet. When driving particularly large capacitive loads a longer soft-start time to prevent current regulation upon charging and a short CR time may offer the best application solution relative to reliability and FET MTF. Physical layout of RSENSE resistor is critical to avoid the possibility of false overcurrent occurrences. Ideally, trace routing between the RSENSE resistors and the IC is as direct and as short as possible with zero current in the sense lines (see Figure 1)..
CORRECT INCORRECT
NOTE: Nominal time-out period = CTIM x 93k.
This IC responds to a severe overcurrent load (defined as a voltage across the sense resistor >150mV over the OC Vth set point) by immediately driving the N-Channel MOSFET gate to 0V in about 10s. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current regulation level; this is the start of the time-out period. Upon a UV condition, the PGOOD signal will pull low when tied high through a resistor to the logic or VDD supply. This pin is a UV fault indicator. For an OC latch-off indication, monitor CTIM, pin 6. This pin will rise rapidly from 1.9V to VDD once the time-out period expires. See Figures 12 through 16 for waveforms relevant to text. The IC is reset after an OC latch-off condition by a low level on the PWRON pin and is turned on by the PWRON pin being driven high.
TO ISEN AND RISET
CURRENT SENSE RESISTOR
FIGURE 1. SENSE RESISTOR PCB LAYOUT
Application Considerations
Design applications where the CR Vth is set extremely low (25mV or less), there is a two-fold risk to consider. * There is the susceptibility to noise influencing the absolute CR Vth value. This can be addressed with a 100pF capacitor across the RSENSE resistor. * Due to common mode limitations of the overcurrent comparator, the voltage on the ISET pin must be 20mV above the IC ground either initially (from ISET*RSET) or before CTIM reaches time-out (from gate charge-up). If this does not happen, the IC may incorrectly report overcurrent fault at start-up when there is no fault. Circuits with high load capacitance and initially low load current are susceptible to this type of unexpected behavior. Do not signal nor pull-up the PWRON input to > 5V. Exceeding 6V on this pin will cause the internal charge pump to malfunction. During the soft-start and the time-out delay duration with the IC in its current limit mode, the VGS of the 6
Using the ISL6116 as a -48V Low Side Hot Swap Power Controller
To supply the required VDD, it is necessary to maintain the chip supply 10V to 16V above the -48V bus. This may be accomplished with a suitable regulator between the voltage rail and pin 5 (VDD). By using a regulator, the designer may ignore the bus voltage variations. However, a low-cost alternative is to use a Zener diode (see Figure 2 for typical 5A load control); this option is detailed in the following. Note that in this configuration the PGOOD feature (pin 7) is not operational as the ISEN pin voltage is always < UV threshold. See Figures 17 through 20 for waveforms relevant to -48V and other high voltage applications.
FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
0.005 1% 1.47k 1% 2k RCL 1.58k 1W 0.01F ISL6116 4 3 2 1
Formulas
Sizing RCL is expressed in Equation 1:
V BUS ( MIN ) - 12 R CL = -----------------------------------------I CHIP (EQ. 1)
LOAD 0.001F
Power Rating of RCL is expressed in Equation 2:
P RCL = I C ( V BUS ( MAX ) - 12 ) (EQ. 2)
DD1 current rating is expressed in Equation 3:
( V BUS ( MAX ) - 12 ) I DD1 = ------------------------------------------------R CL (EQ. 3)
5 0.047F PWRON 6 7 NC DD1 12V 8
Example: A typical -48V supply may vary from -36 to -72V. Therefore: VBUS,MAX = -72V VBUS,MIN = -36V ICHIP = 15mA (Max) Sizing RCL is expressed in Equation 4:
( V BUS ( MIN ) - 12 ) R CL = ----------------------------------------------IC 36 - 12 R CL = -----------------0.015 R CL = 16k [ TypicalValue = 1.58k ]
VBUS
-48V
FIGURE 2. TYPICAL 5A LOAD CONTROL
Biasing the ISL6116
Table 3 gives typical component values for biasing the ISL6116 in a 48V application. The formulas and calculations deriving these values are also shown in the following equations.
TABLE 3. TYPICAL VALUES FOR A -48V HOT SWAP APPLICATION SYMBOL RCL DD1 1.58k, 1W 12V Zener Diode, 50mA Reverse Current PARAMETER
(EQ. 4)
Power rating of RCL is expressed in Equation 5:
P RCL = I C ( V BUS ( MAX ) - 12 ) P RCL = ( 0.015 ) ( 72 - 12 ) P RCL = 0.9W [ TypicalValue = 1W ] (EQ. 5)
When using the ISL6116 to control -48V, a Zener diode may be used to provide the +12V bias to the chip. If a Zener is used then a current limit resistor should also be used. Several items must be taken into account when choosing values for the current limit resistor (RCL) and Zener Diode (DD1): * The variation of the VBUS (in this case, -48V nominal) * The chip supply current needs for all functional conditions * The power rating of RCL. * The current rating of DD1
DD1 current rating is expressed in Equation 6:
( V BUS ( MAX ) - 12 ) I DD1 = ------------------------------------------------R CL ( 72 - 12 ) I DD1 = ----------------------1.58k
(EQ. 6)
I DD1 = 38mA [ TypicalValue = 12Vrating, 50mA reverse current ]
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves
5.0 4.5 SUPPLY CURRENT (mA) ISET CURRENT (A) 20.2 20.0 19.8 19.6
4.0 3.5
3.0
19.4 19.2 19.0 0
2.5 2.0 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (C)
FIGURE 3. VDD BIAS CURRENT
FIGURE 4. ISET SOURCE CURRENT
20.50 CTIM = 0V, CURRENT SOURCE (A) 20.32 CTIM - 0V CTIM OC VOLTAGE THRESHOLD (V)
1.89 1.88
20.16 20.00
1.87 1.86 1.85
19.82
19.66 19.50 0 10 20 30 40 50 60 70 TEMPERATURE (C) 80 90 100
1.84
1.83 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C)
FIGURE 5. CTIM CURRENT SOURCE
9.76 4.37 ISL6116, 5V UV THRESHOLD (V) 2.70
FIGURE 6. CTIM OC VOLTAGE THRESHOLD
1.860 ISL6120, 2.5V UV THRESHOLD (V) ISL6117
ISL6115, 12V UV THRESHOLD (V)
ISL6116 ISL6115 9.75
4.36
ISL6117, 3.3V UV THRESHOLD (V)
2.65
1.855
ISL6120 2.60 0 1.850 100
9.74 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C)
4.35 100
10
20
30
40
50
60
70
80
90
TEMPERATURE (C)
FIGURE 7. ISL6115, ISL6116 UV THRESHOLD
FIGURE 8. ISL6117, ISL6120 UV THRESHOLD
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves
10.2 GATE CHARGE CURRENT (A) 10.1
(Continued)
17.200 17.183 17.166 17.150 12.00 11.99 ISL6116,17,20 GATE DRIVE (V)
10.0 9.9
ISL6115, GATE DRIVE (V)
11.98 11.97
9.8
17.133 17.116
11.96
9.7
11.95 11.94 100
9.6 0
17.100 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (C) TEMPERATURE (C)
FIGURE 9. GATE CHARGE CURRENT
FIGURE 10. GATE DRIVE VOLTAGE, VDD = 12V
8.5 VDD LO TO HI
8.4 POWER ON RESET (V)
8.3
GATE VOUT PGOOD
8.2 IOUT
8.1
VDD HI TO LO
PWRON 8.0 0
10
20
30
40
50
60
70
80
90
100 5V/DIV 0.5A/DIV 1ms/DIV
TEMPERATURE (C)
FIGURE 11. POWER-ON RESET VOLTAGE THRESHOLD
FIGURE 12. ISL6115 +12V TURN-ON
GATE PGOOD
GATE PWRON VOUT VOUT IOUT PGOOD
IOUT
CTIM
2V/DIV 0.5A/DIV 1ms/DIV
5V/DIV 0.5A/DIV 1ms/DIV
FIGURE 13. ISL6116 +5V TURN-ON
FIGURE 14. ISL6115 `LOW' OVERCURRENT RESPONSE
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
Typical Performance Curves
(Continued)
IOUT VOUT PGOOD GATE CTIM IOUT GATE VOUT PGOOD 5V/DIV 0.5A/DIV 1ms/DIV 2V/DIV 0.5A/DIV 1ms/DIV CTIM
FIGURE 15. ISL6115 `HIGH' OVERCURRENT RESPONSE
FIGURE 16. ISL6116 `HIGH' OVERCURRENT RESPONSE
VDRAIN 10V/DIV +50V
IOUT 1A/DIV
VDRAIN 10V/DIV 0V
IOUT 1A/DIV
VGATE 5V/DIV VGATE 5V/DIV
PWRON 5V/DIV EN 5V/DIV 0V 5ms/DIV
0V
0V 5ms/DIV
-50V
FIGURE 17. +50V LOW SIDE SWITCHING CGATE = 100pF
FIGURE 18. -50V LOW SIDE SWITCHING CGATE = 1000pF
+350V VDRAIN 50V/DIV
IOUT 1A/DIV
+350V VDRAIN 50V/DIV
IOUT 1A/DIV
VGATE 5V/DIV
VGATE 5V/DIV
PWRON 5V/DIV
PWRON 5V/DIV 0V 0V 2ms/DIV
2ms/DIV
FIGURE 19. +350V LOW SIDE SWITCHING CGATE = 100pF
FIGURE 20. +350V LOW SIDE SWITCHING CGATE = 1000pF
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
ISL6115EVAL1Z Board
The ISL6115EVAL1Z is default provided as a +12V high side switch controller with the CR level set at ~1.5A. See Figure 21 for ISL6115EVAL1Z schematic and Table 4 for BOM. Bias and load connection points are provided along with test points for each IC pin. With J1 installed the ISL6115 will be biased from the +12V supply (VIN) being switched. Connect the load to VLOAD+. PWRON pin pulls high internally enabling the ISL6115 if not driven low via PWRON test point or J2. With R3 = 750 the CR Vth is set to 15mV and with the 10m sense resistor (R1) the ISL6115EVAL1Z has a nominal CR level of 1.5A. The 0.01F delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event. Also included with the ISL6115EVAL1Z board are one each of the ISL6116, ISL6117 and ISL6120 for evaluation of those ICs in a high side application. Remove J1 and provide a separate +12V IC bias supply via VBIAS test point. Reconfiguring the ISL6115EVAL1Z board for a higher CR level can be done by changing the RSENSE and/or RISET resistor values as the provided FET is rated for a much higher current.
Bias and load connection points are provided in addition to test points, TP1 to TP8 for each IC pin. The terminals, J1 and J4 are for the bus voltage and return, respectively, with the more negative potential being connected to J4. With the load between terminals J2 and J3 the board is now configured for evaluation. The device is enabled through LOGIN, TP9 with a TTL signal. ISL6116EVAL1 includes a level shifting circuit with an opto-coupling device for the PWRON input so that standard TTL logic can be translated to the -V reference for chip control. When controlling a positive voltage, PWRON can be accessed at TP8. The ISL6116EVAL1 is provided with a high voltage linear regulator for convenience to provide chip bias from 24V to 350V. This can be removed and replaced with the zener and resistor bias scheme as discussed earlier. High voltage regulators and power discrete devices are no longer available from Intersil but can be purchased from other semiconductor manufacturers. Reconfiguring the ISL6116EVAL1 board for a higher CR level can be done by changing the RSENSE and RISET resistor values as the provided FET is 75A rated. If evaluation at >60V, an alternate FET must be chosen with an adequate BVDSS.
ISL6116EVAL1 Board
The ISL6116EVAL1 is default configured as a negative voltage low side switch controller with a ~2.4A CR level. See Figure 22 for ISL6116EVAL1 schematic and Table 4 for BOM and component description. This basic configuration is capable of controlling both larger positive or negative potential voltages with minimal changes.
HI J2
LOAD C1
J3 LO Q2 R1 R2 J4 -VBUS
J1 VLOAD+ VOUT R3 1 R1 2 3 U1 R2 C1 J1 VIN +12V VBIAS 4 C2 ISL6115 U2 8 7 6 5 C3 R4 AGND +VBUS
R7
J2 PWRON PGOOD CTIM C3
4 5
ISL6116 U1 6 7 8
3
2
1 PWRON TP8 LOGIN TP9 R8 R10
R G 1 R6 R11
VBIAS
D2
DD1 3.3V
R5 R9 OFF 0V to 5V OT1 ON
FIGURE 21. ISL6115EVAL1Z HIGH SIDE SWITCH APPLICATION
FIGURE 22. ISL6116EVAL1 NEGATIVE VOLTAGE LOW SIDE CONTROLLER
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FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120
TABLE 4. BILL OF MATERIALS, ISL6115EVAL1Z, ISL6116EVAL1 COMPONENT DESIGNATOR ISL6115EVAL1Z U1 R1 R2 R3 R4 C1 C2 C3 J1 N-FET Load Current Sense Resistor Gate Stability Resistor Overcurrent Voltage Threshold Set Resistor PGOOD Pull up Resistor Gate Timing Capacitor IC Decoupling Capacitor Time Delay Set Capacitor Bias Voltage Selection Jumper 11.5m, 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent WSL-2512 10m 1W Metal Strip Resistor 20 0603 Chip Resistor 750 0603 Chip Resistor (Vth = 15mV) 10k 0603 Chip Resistor 0.001F 0402 Chip Capacitor (<2ms) 0.1F 0402 Chip Capacitor 0.01F 0402 Chip Capacitor (1ms) Install if switched rail voltage is = +12V. Remove and provide separate +12V bias voltage to U2 via VBIAS if ISL6116, ISL6117 or ISL6120 is being evaluated. Install J2 to disable U2. Connects PWRON to GND. COMPONENT NAME COMPONENT DESCRIPTION
J2 ISL6116EVAL1 Q2 R1 R2 R7 C1 C3 R5 D2 DD1 OT1 R8 R9 R10 RG1 R6 R11
PWRON Disable
N-FET Load Current Sense Resistor Overcurrent Voltage Threshold Set Resistor Gate to Drain Resistor Gate Timing Capacitor IC Decoupling Capacitor LED Series Resistors Fault Indicating LEDs Fault Voltage Dropping Diode PWRON Level Shifting Opto-Coupler Level Shifting Bias Resistor Level Shifting Bias Resistor Level Shifting Bias Resistor HIP5600IS Linear Regulator RF1 Linear Regulator RF2
10m, 80V, 75A N-Channel Power MOSFET or equivalent WSL-2512 10m 1W Metal Strip Resistor 1.21k 805 Chip Resistor (Vth = 24mV) 2k 805 Chip Resistor 0.001F 805 Chip Capacitor (<2ms) 0.1F 805 Chip Capacitor 2.32k 805 Chip Resistor Low Current Red SMD LED 3.3V Zener Diode, SOT-23 SMD 350mW PS2801-1 NEC 2.32k 805 Chip Resistor 1.18k 805 Chip Resistor 200 805 Chip Resistor High Voltage Linear Regulator 1.78k 805 Chip Resistor 15k 805 Chip Resistor
12
FN9100.7 April 29, 2010
ISL6115, ISL6116, ISL6117, ISL6120 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E e H
C
e
B 0.25(0.010) C A M B S M
A1 0.10(0.004)
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
a
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN9100.7 April 29, 2010

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